HD6417727BP160CV Datasheet, PDF (443/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
…
0
…
Initial value: —
—
—
—
…
—
R/W: R/W R/W R/W R/W
…
R/W
The DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit read/write registers that
specify the destination address of a DMA transfer. These registers include count functions, and
during a DMA transfer, these registers indicate the next destination address.
To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary.
When transferring data in 16-byte units, always set a value at a 16-byte boundary (16n address) as
the destination address. If any other address is specified, correct operation is not guaranteed.
Initial values are undefined after a reset. The previous value is held in standby mode.
Rev.6.00 Mar. 27, 2009 Page 385 of 1036
REJ09B0254-0600