HD6417727BP160CV Datasheet, PDF (541/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 17 Serial Communication Interface (SCI)
Figures 17.2 to 17.4 show the block diagrams of the SCI I/O port.
SCI pin I/O and data control is performed by bits 3 to 0 of SCPCR and bits 1 and 0 of SCPDR. For
details, see section 17.2.8, Port SC Control Register (SCPCR)/Port SC Data Register (SCPDR).
SCPT[1]/SCK0
Reset
R
D
SCP1MD0
Q
C
PCRW
Reset
R
QD
SCP1MD1
C
PCRW
Reset
R
QD
SCP1DT1
C
PDRW
Internal data bus
SCI
Clock input enable
Output enable
Serial clock output
PDRR*
Legend:
PDRW: SCPDR write
PDRR: SCPDR read
PCRW: SCPCR write
Serial clock input
Note: * When reading the SCK0 pin, clear the C/A bit in SCSMR and the CKE1 and CKE0
bits in SCSCR to 0, and set the SCP1MD1 bit in SCPCR to 1 (see section 17.2.8).
Figure 17.2 SCPT[1]/SCK0 Pin
Rev.6.00 Mar. 27, 2009 Page 483 of 1036
REJ09B0254-0600