HD6417727BP160CV Datasheet, PDF (505/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 15 Timer (TMU)
15.2.2 Timer Control Register (TCR)
The timer control registers (TCR) are 16-bit read/write registers that control the timer counters
(TCNT) and interrupts. The TMU has a total of three TCR registers, one for each channel.
The TCR registers control the interrupt generated when the flag that indicates the timer counter
(TCNT) underflow has been set to 1, and select the counter clock. When an external clock has
been selected, the clock edge can also be selected.
TCR is initialized to H'0000 by a power-on reset or manual reset. In standby mode, it is not
initialized and retains the value.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
—
UNIE
—
0
0
0
R
R/W
R
3
2
1
0
— TPSC2 TPSC1 TPSC0
0
0
0
0
R
R/W R/W R/W
Bits 15 to 9, 7, 6, 4, and 3—Reserved: These bits are always read as 0 and should only be written
with 0.
Bit 8—Underflow Flag (UNF): This is a status flag that indicates that TCNT underflowed.
Bit 8: UNF
Description
0
TCNT has not underflowed.
Clear condition: When 0 is written to UNF
(Initial value)
1
TCNT has underflowed (H'00000000 → H'FFFFFFFF).
Setting condition: When TCNT underflows*
Note: * When a write of 1 is provided to UNF, it is not modified and the previous value is retained.
Rev.6.00 Mar. 27, 2009 Page 447 of 1036
REJ09B0254-0600