HD6417727BP160CV Datasheet, PDF (724/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
Bit 2—Rx FIFO Full Interrupt (RFF)
Bit 2: RFF
0
1
Description
No interrupt
Rx FIFO full interrupt
(Initial value)
Set condition:
1. Specified size with FFSZ(ACTR1) of receive data is accumulated into FIFO.
Clear condition:
1. Reset
2. Number of data in FIFO becomes smaller than the size that is indicated with FFSZ (ACTR1).
3. RE bit (ACTR1) is set to 0.
Bit 1—TX FIFO Half Size Empty (THE)
Bit 1: THE
0
1
Description
Normal state
Tx FIFO Half Size Interrupt
(Initial value)
Set condition:
1. Reset
2. Number of valid data in FIFO becomes smaller than the half of the size that is indicated with
FFSZ.
3. TE bit (ACTR1) is set to 0
(THEM is automatically masked in case 3.)
Clear condition:
1. Number of valid data in FIFO becomes greater than the half of the size that is indicated by
FFSZ.
Rev.6.00 Mar. 27, 2009 Page 666 of 1036
REJ09B0254-0600