HD6417727BP160CV Datasheet, PDF (60/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 1 Overview and Pin Functions
Table 1.1 SH7727 Features
Item
CPU
Features
• Original Renesas SuperH architecture
• Object code level compatible with SH-1, SH-2 and SH-3
• 32-bit internal data bus
• General-register
⎯ Sixteen 32-bit general registers (eight 32-bit shadow registers)
⎯ Eight 32-bit control registers
⎯ Four 32-bit system registers
• RISC-type instruction set
⎯ Instruction length: 16-bit fixed length to improve code efficiency
⎯ Load-store architecture
⎯ Delayed branch instructions
⎯ Instruction set based on C language
• Instruction execution time: one instruction/cycle for basic instructions
• Logical address space: 4 Gbytes
• Space identifier ASID: 8 bits, 256 logical address space
• Five-stage pipeline
Rev.6.00 Mar. 27, 2009 Page 2 of 1036
REJ09B0254-0600