HD6417727BP160CV Datasheet, PDF (266/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): Selects the instruction
fetch cycle or data access cycle as the bus cycle of the channel A break condition.
Bit 5: IDA1
0
1
Bit 4: IDA0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
The break condition is the instruction fetch cycle
The break condition is the data access cycle
The break condition is the instruction fetch cycle or data access
cycle
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the
bus cycle of the channel A break condition.
Bit 3: RWA1
0
1
Bit 2: RWA0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
The break condition is the read cycle
The break condition is the write cycle
The break condition is the read cycle or write cycle
Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle
for the channel A break condition.
Bit 1: SZA1
0
1
Bit 0: SZA0
0
1
0
1
Description
The break condition does not include operand size
(Initial value)
The break condition is byte access
The break condition is word access
The break condition is longword access
Rev.6.00 Mar. 27, 2009 Page 208 of 1036
REJ09B0254-0600