HD6417727BP160CV Datasheet, PDF (159/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

H'00000000
Section 3 Memory Management Unit (MMU)
H'00000000
2-Gbyte virtual space,
cacheable
Area P0
(write-back/write-through)
2-Gbyte virtual space,
cacheable
Area U0
(write-back/write-through)
H'80000000
0.5-Gbyte fixed physical
space, cacheable
(write-back/write-through)
H'80000000
Area P1
H'A0000000
0.5-Gbyte fixed
physical space,
non-cacheable
Area P2
H'C0000000
0.5-Gbyte virtual space,
cacheable
(write-back/write-through)
Area P3
H'E0000000
H'FFFFFFFF
0.5-Gbyte control space,
non-cacheable
Area P4
H'FFFFFFFF
Address error
Address error
Area Uxy
(present
only when
SR.DSP=1)
Privileged mode
User mode
Figure 3.2 Logical Address Space Mapping
Physical Address Space: The SH7727 supports a 32-bit physical address space, but the upper 3
bits are actually ignored and treated as a shadow. See section 12, Bus State Controller (BSC), for
details.
Address Translation: When the MMU is enabled, the logical address space is divided into units
called pages. Physical addresses are translated in page units. Address translation tables in external
memory hold information such as the physical address that corresponds to the logical address and
memory protection codes. When an access to an area other than P4 occurs, if the accessed logical
address belongs to area P1 or P2 there is no TLB access and the physical address is uniquely
defined. If it belongs to area P0, P3 or U0, the TLB is searched by logical address and, if that
logical address is registered in the TLB, the access hits the TLB. The corresponding physical
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