HD6417727BP160CV Datasheet, PDF (506/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 15 Timer (TMU)
Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt
generation when the status flag (UNF) that indicates TCNT underflow has been set to 1.
Bit 5: UNIE
0
1
Description
Interrupt due to UNF (TUNI) is disabled.
Interrupt due to UNF (TUNI) is enabled.
(Initial value)
Bits 2 to 0—Timer Prescalers 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT count
clock.
Bit 2: TPSC2
0
1
Bit 1: TPSC1
0
1
0
1
Bit 0: TPSC0
0
1
0
1
0
1
0
1
Description
Counts on peripheral clock Pφ/4 (Initial value)
Counts on peripheral clock Pφ/16
Counts on peripheral clock Pφ/64
Counts on peripheral clock Pφ/256
Counts on on-chip RTC clock outputs (RTCCLK)
Reserved (Setting disabled)
Reserved (Setting disabled)
Reserved (Setting disabled)
15.2.3 Timer Constant Register (TCOR)
The TMU has a total of three TCOR registers, one for each channel. The TCOR registers are 32-
bit read/write registers that specify a value to be set to the TCNT counter after a TCNT counter
underflow occurred.
TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset. In standby mode, it is
not initialized and retains the value.
Rev.6.00 Mar. 27, 2009 Page 448 of 1036
REJ09B0254-0600