HD6417727BP160CV Datasheet, PDF (838/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
25.2.11 LCDC Horizontal Sync Signal Register (LDHSYNR)
LDHSYNR specifies the timing of the generation of the horizontal (scan direction) sync signals
(CL1/Hsync) for the LCD module.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HSYN HSYN HSYN HSYN —
—
—
— HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP
W3 W2 W1 W0
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 12—Horizontal Sync Signal Width (HSYNW): Sets the width in characters of the
horizontal sync signals (CL1 and Hsync).
Subtract 1 from the setting (0 to 15 (H'F)).
Example: For a horizontal sync signal width of 8 dots
HSYNW = (8 dots/8 dots/character) – 1 = 0 = H'0
Bits 7 to 0—Horizontal Sync Signal Output Position (HSYNP): Sets the output position in
characters of the horizontal sync signals.
Subtract 1 from the setting (0 to 255 (H'FF)).
The following conditions must be satisfied: HTCN >= HSYNP + HSYNW + 1
HSYNP >= HDCN + 1
Example: For an LCD module with a width of 640 pixels
HSYNP = [(640/8) + 1] – 1 = 80 = H'50
In this case, the horizontal sync signal is active from the 648th through the 655th dot.
Rev.6.00 Mar. 27, 2009 Page 780 of 1036
REJ09B0254-0600