HD6417727BP160CV Datasheet, PDF (230/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 7 Interrupt Controller (INTC)
when the RTC is not used, interruption by means of IRL interrupts cannot be performed in standby
mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt processing starts. Correct operation cannot be guaranteed if the level is not maintained.
However, the priority level can be changed to a higher one.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRL interrupt
processing.
7.2.4 PINT Interrupt
PINT interrupts are input by priority from pins PINT0 to PINT15 with a level. The priority level
can be set by priority setting registers D (IPRD) in a range from levels 0 to 15, in the unit of
PINT0 to PINT7 or PINT8 to PINT15.
The PINT interrupt level should be held until the interrupt is accepted and interrupt handling is
started.
The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by PINT interrupt
processing.
PINT interrupts can wake the chip up from the standby state when the relevant interrupt level is
higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator is used).
7.2.5 On-Chip Supporting Module Interrupts
On-chip supporting module interrupts are generated by the following fourteen modules:
• Timer unit (TMU)
• Realtime clock (RTC)
• Serial communication interface (SCI, SCIF)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Direct memory access controller (DMAC)
• Analog-to-digital converter (ADC)
• PC Card controller (PCC)
• OHCI compliant USB HOST controller (USBH)
• USB function controller (USBF)
• AFE interface (AFEIF)
• LCD controller (LCDC)
Rev.6.00 Mar. 27, 2009 Page 172 of 1036
REJ09B0254-0600