HD6417727BP160CV Datasheet, PDF (59/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 1 Overview and Pin Functions
Section 1 Overview and Pin Functions
1.1 Features
The SH7727 is a single-chip RISC microprocessor that integrates a 32-bit RISC-type SuperH
RISC engine architecture CPU with digital signal processing (DSP) extension as its core that has a
cache memory, an on-chip X/Y memory, and a memory management unit (MMU) as well as
peripheral functions required for system configuration. The SH7727 includes data protection,
virtual memory, and other functions provided by incorporating an MMU into a SuperH Series
microprocessor (SH-1 or SH-2).
The SH7727 chip has the on-chip X/Y memory with large capacitance, on-chip DSP module, and
emulator support. The provision of on-chip DSP functions enables applications that previously
required the use of two chips—a microprocessor and a DSP—to be implemented with a single
chip.
High-speed data transfers with a direct memory access controller (DMAC) and an external
memory access support function enables direct connection to each memory. The SH7727
microprocessor also supports an infrared communication function, a stereo audio recording and
playback function, a USB host controller, a function controller, an LCD controller, a PCMCIA
interface, an A/D converter, and a D/A converter.
The USB host controller and LCD controller have bus master functions, so that data supplied from
an external memory (area 3) can be freely processed. Because the USB host controller, in
particular, conforms to Open HCI standards, it is extremely easy to transfer data from the PC of a
device driver or other devices. Also, low-power operation suitable for battery operation is possible
because the LCD controller continues to display even in sleep mode.
An internal USB transceiver is also provided, eliminating the need for attachments.
A powerful built-in power management function keeps power consumption low, even during high-
speed operation. In particular, power consumption can be significantly reduced by halting the X/Y
memory. Because the LSI operates at a maximum speed eight times of the speed at which the
system operates, it is ideal for electronic devices, which require both high speed and low power
consumption.
The features of this LSI are listed in table 1.1. The specifications of this LSI are listed in table 1.2.
Rev.6.00 Mar. 27, 2009 Page 1 of 1036
REJ09B0254-0600