HD6417727BP160CV Datasheet, PDF (590/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 17 Serial Communication Interface (SCI)
Serial Data Transmission (Clock Synchronous Mode):
Figure 17.19 shows a sample flow chart for serial data transmission. After enabling the SCI
transmission, transmit serial data following the procedure shown below:
Start transmission
Read TDRE bit in SCSSR
(1)
TDRE = 1?
No
Yes
Write transmission data to SCTDR
and clear TDRE bit in SCSSR to 0
All data transmitted?
No ₍₂₎
Yes
Read TEND bit in SCSSR
(1) SCI status check and transmit
data write:
Read the serial status register
(SCSSR), check that the TDRE
bit is 1, then write transmit data
in the transmit data register
(SCTDR) and clear TDRE to 0.
(2) To continue transmitting serial
data:
Read the TDRE bit to check
whether it is safe to write (if it
reads 1); if so, write data in
SCTDR, then clear TDRE to 0.
TEND = 1?
No
Yes
Clear TE bit in SCSCR to 0
End transmission
Figure 17.19 Sample Serial Transmission Flowchart
Rev.6.00 Mar. 27, 2009 Page 532 of 1036
REJ09B0254-0600