HD6417727BP160CV Datasheet, PDF (675/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
Bit 9—Transmit Enable (TXE): Setting of this bit becomes effective when next frame starts (at
the rising edge of frame synchronize signal)and data are stored in transmit FIFO. After the setting
“1” to this bit becomes effective, SIOF submit the transmit request according to the TFWM bit of
SIFCTR register. When data is sets to transmit FIFO, transmit data is transfer from TXD_SIO.
This bit is initialized at transmit reset.
Bit 9: TXE
0
1
Description
Disable to transmit data from TXD_SIO (outputs 1)
Enable to transmit data from TXD_SIO
(Initial value)
Bit 8—Receive Enable (RXE): Setting of this bit is effective when next frame starts (at the rising
edge of frame synchronizing signal). After the setting “1” to this bit becomes effective, SIOF
begins to receive the data from RXD_SIO. When data is sets to the receive FIFO, SIOF submits
the request to transfer according to RFWM bit of SIFCTR register. This bit is initialized at receive
reset.
Bit 8: RXE
0
1
Description
Disable to receive data from RXD_SIO
Enable to receive data from RXD_SIO
(Initial value)
Bit 1—Transmitting Operation Reset (TXRST): Setting to this bit becomes effective
immediately. After the setting 1 to this bit becomes effective, SIOF change transmit data from
TXD_SIO to 1 and initializes the following registers.
1. SITDR register
2. Transmit FIFO write pointer and read pointer
3. TCRDY, TFEMP, and TDREQ bits of SISTR register
4. TXE bit
SIOF is cleared automatically when this bit completes the reset, so 0 is always read from this bit.
Bit 1: TXRST
0
1
Description
Transmitting operation is not reset
Transmitting operation is reset
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 617 of 1036
REJ09B0254-0600