HD6417727BP160CV Datasheet, PDF (97/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

DSP type fixed point
39
With guard bits S
Without guard bits
39
Multiplier input
31 30
31 30
S
31 30
S
DSP type integer
39
With guard bits S
32 31
31
Without guard bits
S
Shift amount for
31
arithmetic shift (PSHA)
Shift amount for
31
logical shift (PSHL)
16 15
16 15
16 15
22 16 15
S
21 16 15
S
DSP type logical
CPU type integer
Longword
39
31
31
S
16 15
Section 2 CPU
0
−2⁸ to +2⁸ − 2^−31
0
−1 to +1 − 2^−31
0
−1 to +1 − 2^−15
0
−2²³ to +2²³ − 1
0
−2¹⁵ to +2¹⁵ − 1
0
−32 to +32
0
−16 to +16
0
0
−2³¹ to +2³¹ − 1
S: Sign bit
: Binary point
: Does not affect the operations
Figure 2.10 Data Format
Shift amount for arithmetic shift (PSHA) instruction has 7 bits filed that could represent –64 to
+63, however –32 to +32 is the valid number for the operation. Also the shift amount for logical
shift operation has 6-bits field, however –16 to +16 is the valid number for the instruction.
Rev.6.00 Mar. 27, 2009 Page 39 of 1036
REJ09B0254-0600