HD6417727BP160CV Datasheet, PDF (260/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 7 Interrupt Controller (INTC)
Interrupt
acceptance
Start of interrupt
processing
0.5 × Icyc
+ 0.5 × Bcyc
+ 2 × Pcyc
IRL
5 × Icyc
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
IF ID EX EX EX EX
IF
First instruction of interrupt
handler
IF ID EX
IF: Instruction fetch: Instruction is fetched from memory in which program is stored.
ID: Instruction decode: Fetched instruction is decoded.
EX: Instruction execution: Data operation and address calculation are performed in
accordance with result of decoding.
Figure 7.4 Example of Pipeline Operations when IRL Interrupt is Accepted
Rev.6.00 Mar. 27, 2009 Page 202 of 1036
REJ09B0254-0600