HD6417727BP160CV Datasheet, PDF (289/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
on Y memory space. The X/Y-memory space is changed by a mode specification.
Break Condition Specified to a DMAC Data Access Cycle
1. Register specifications
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
• Channel A
Address: H'00314156, Address mask: H'00000000, ASID: H'80
Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition)
• Channel B
Address: H'00055555, Address mask: H'00000000, ASID: H'70
Data:
H'00000078, Data mask: H'0000000F
Bus cycle: DMAC/data access/write/byte
On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles.
On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in
address H'00055555.
8.3.9 Usage Notes
1. Only CPU can read/write UBC registers.
2. UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes in specification of sequential break are described below:
(1) A condition match occurs when B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs even if a bus cycle, in which an A-channel match and a channel B match
occur simultaneously, is set.
(2) Since the CPU has a pipeline configuration, the pipeline determines the order of an
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
(3) When the bus cycle condition for channel A is specified as a break before execution
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows.
A break is issued and condition match flags in BRCR are set to 1, when the bus cycle
conditions both for channels A and B match simultaneously.
Rev.6.00 Mar. 27, 2009 Page 231 of 1036
REJ09B0254-0600