HD6417727BP160CV Datasheet, PDF (1040/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 32 Electrical Characteristics
32.3.11 SIOF Module Signal Timing
Table 32.14 SIOF Module Signal Timing
Conditions: V_CCQ = 2.6 to 3.6 V, V_CC = 1.60 to 2.05 V, AV_CC = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item
Symbol Min
SIOMCLK clock input cycle time
t_MCYC
30
SIOMCLK input high-level width
t_MWH
0.4 × t_MCYC
SIOMCLK input low-level width
t_MWL
0.4 × t_MCYC
SCK_SIO clock cycle time
t_SICYC
2 × t_PCYC
SCK_SIO output high-level width t_SWHO
0.4 × t_SICYC
SCK_SIO output low-level width
t_SWLO
0.4 × t_SICYC
SIOFSYNC output delay time
t_FSD
—
SCK_SIO input high-level width
t_SWHI
0.4 × t_SICYC
SCK_SIO input low-level width
t_SWLI
0.4 × t_SICYC
SIOFSYNC input setup time
t_FSS
20
SIOFSYNC input hold time
t_FSH
20
TXD_SIO output delay time
t_STDD
—
RXD_SIO input setup time
t_SRDS
20
RXD_SIO input hold time
t_SRDH
20
Note: t_PCYC is the cycle time (ns) of the peripheral clock (Pφ)
Max
—
—
—
—
—
—
20
—
—
—
—
20
—
—
Unit Figure
ns 32.52
ns 32.52
ns 32.52
ns 32.53 to 32.57
ns 32.53 to 32.56
ns 32.53 to 32.56
ns 32.53 to 32.56
ns 32.57
ns 32.57
ns 32.57
ns 32.57
ns 32.53 to 32.57
ns 32.53 to 32.57
ns 32.53 to 32.57
t_MCYC
SIOMCLK
t_MWH
t_MWL
Figure 32.52 SIOMCLK Input Timing
Rev.6.00 Mar. 27, 2009 Page 982 of 1036
REJ09B0254-0600