HD6417727BP160CV Datasheet, PDF (172/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 3 Memory Management Unit (MMU)
the physical address is recorded in a different entry from that of the index number indicated by the
physical address in the cache address array.
Note:
When multiple address information items use the same physical memory to provide for
future expansion of the SuperH RISC engine family, it is recommended that VPN[20:10]
be made equal. Also, the same physical addresses should not be used with different page
size address conversion information.
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Logical address 1 H'00000000 → physical address H'00000C00
Logical address 2 H'00000C00 → physical address H'00000C00
Logical address 1 is recorded in cache entry H'00, and logical address 2 in cache entry H'C0. Since
two logical addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
logical address.
Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same as a physical
address already used in another TLB entry, it should be recorded in such a way that physical
address bits 11 and 10 are the same.
Rev.6.00 Mar. 27, 2009 Page 114 of 1036
REJ09B0254-0600