HD6417727BP160CV Datasheet, PDF (846/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
Bits 1 and 0—LCD Module Power-Supply Input State (LPS1 and LPS0): Indicate the power-
supply input state of the LCD module when using the power-supply control function.
Bit 1
LPS1
0
1
Bit 0
LPS0
0
1
Description
LCD module power off
LCD module power on
(Initial value)
25.2.18 LCDC Power-Supply Sequence Period Register (LDPSPR)
LDPSPR controls the power supply circuit that provides power to the LCD module. The timing to
start outputting the timing signals to the VEPWC and VCPWC pins is specified.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ONA3 ONA2 ONA1 ONA0 ONB3 ONB2 ONB1 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0
Initial value: 1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 12—LCDC Power-On Sequence Period (ONA): Set the period from VCPWC
assertion to starting output of the display data (LCDD) and timing signals (FLM, CL1, CL2, and
M/DISP) in the power-on sequence of the LCD module in frame units.
This period is the (a) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting.
Bits 11 to 8—LCDC Power-On Sequence Period (ONB): Set the period from starting output of
the display data (LCDD) and timing signals (FLM, CL1, CL2, and DISP/M) to the VEPWC
assertion in the power-on sequence of the LCD module in frame units.
This period is the (b) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting.
Bits 7 to 4—LCDC Power-Off Sequence Period (OFFE): Set the period from VEPWC negation
to stopping output of the display data (LCDD) and timing signals (FLM, CL1, CL2, and DISP/M)
in the power-off sequence of the LCD module in frame units.
This period is the (e) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting.
Bits 3 to 0—LCDC Power-Off Sequence Period (OFFF): Set the period from stopping output
of the display data (LCDD) and timing signals (FLM, CL1, CL2, and DISP/M) to VCPWC
negation to in the power-off sequence of the LCD module in frame units.
This period is the (f) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting.
Rev.6.00 Mar. 27, 2009 Page 788 of 1036
REJ09B0254-0600