HD6417727BP160CV Datasheet, PDF (768/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 23 USB Function Controller
(3) Data Stage (Control-Out)
USB function
OUT token reception
Application
1 written
to USBTRG/EP0s
RDFN?
Yes
No
NACK
Data reception from host
ACK
Set EP0o receive-end
flag to 1
(USBIFR0/EP0o TS = 1)
Interrupt request
Clear EP0o receive-end flag
(USBIFR0/EP0o TS = 0)
OUT token reception
1 written
to USBTRG/EP0o
RDFN?
Yes
No
NACK
Read data from USBEP0o
data size register
(USBEPSZ0o)
Read data from USBEP0o
data register (USBEPDR0o)
Write 1 to EP0o read-end bit
(USBTRG/EP0o RDFN = 1)
Figure 23.7 Data Stage Operation (Control-Out)
The application analyzes command data from the host in the setup stage and decides the following
data stage direction. As a result of command data analysis, when the data stage is out-transfer,
data from the host is waited. After data reception (USBIFR0/EP0o TS = 1), data is read from
FIFO. Applications then write 1 to the EP0o read-end bit, make reception FIFO empty, and wait
for the next data reception.
The end of the data stage is decided by transferring in-token by the host and entering the status
stage.
Rev.6.00 Mar. 27, 2009 Page 710 of 1036
REJ09B0254-0600