HD6417727BP160CV Datasheet, PDF (680/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
value of RFWM bit of SIMDR register. SIOF issues a receive interrupt if the interrupt issuing is
allowed for this bit.
Bit 8: RDREQ
0
1
Description
Effective data in receive FIFO does not exceed setting of RFWM bit of SIMDR
register
(Initial value)
Effective data in receive FIFO exceeds setting of RFWM bit of SIMDR register
Bit 4—Frame Synchronization Error (FSERR): Frame synchronization error shows that next
frame synchronize timing has come before data or control command are transferred. When frame
synchronization error has occurred , SIOF transmits or receives data to the slots that are enable to
transmit or receive data.
This bit becomes effective when 1 is written to TXE bit or RXE bit of SICTR register. This bit is
cleared when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing
is allowed to this bit.
Bit 4: FSERR
0
1
Description
Frame synchronization error does not occur
Frame synchronization error occurs
(Initial value)
Bit 3—Transmit FIFO Over Run (TFOVR): Transmit FIFO overrun shows that data are written
to SITDR register when transmit FIFO is full. Written data is ignored when Transmit FIFO over
run happens.
This bit is effective when 1 is written to TXE bit of SICTR register. This bit is cleared when 1 is
written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this
bit.
Bit 3: TFOVR
0
1
Description
Transmit FIFO over run does not occur
Transmit FIFO over run occurs
(Initial value)
Bit 2—Transmit FIFO Under Run (TFUDR):Transmit FIFO under run shows that the load by
data transfer from FIFO has occurred when transmit FIFO is empty.
SIOF repeats to send the data that was sent before when this under run has occurred.
Rev.6.00 Mar. 27, 2009 Page 622 of 1036
REJ09B0254-0600