HD6417727BP160CV Datasheet, PDF (367/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 9, 3, and 2—Area 5 OE/WE Negate Address Delay(A5TEH2, A5TEH1, and A5TEH0):
The A5TEH bits specify the OE/WE negate address delay time for the PCMCIA interface
connected area 5.
Bit 9:
A5TEH2
0
1
Bit 3:
A5TEH1
0
1
0
1
Bit 2:
A5TEH0
0
1
0
1
0
1
0
1
Description
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
Bits 8, 1, and 0—Area6 OE/WE Negate Address Delay (A6TEH2, A6TEH1, and A6TEH0):
The A6TEH bits specify the OE/WE negate address delay time for the PCMCIA interface
connected to area 6.
Bit 8:
A6TEH2
0
1
Bit 1:
A6TEH1
0
1
0
1
Bit 0:
A6TEH0
0
1
0
1
0
1
0
1
Description
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 309 of 1036
REJ09B0254-0600