HD6417727BP160CV Datasheet, PDF (545/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 17 Serial Communication Interface (SCI)
17.2 Register Descriptions
17.2.1 Receive Shift Register (SCRSR)
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—
The receive shift register (SCRSR) receives serial data.
Data input at the RxD0 pin is loaded into the SCRSR in the order received, LSB (bit 0) first,
converting the data to parallel form. When one byte has been received, it is automatically
transferred to the SCRDR.
The CPU cannot read or write the SCRSR directly.
17.2.2 Receive Data Register (SCRDR)
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
The receive data register (SCRDR) stores serial receive data.
The SCI completes the reception of one byte of serial data by moving the received data from the
receive shift register (SCRSR) into the SCRDR for storage. The SCRSR is then ready to receive
the next data.
This double buffering allows the SCI to receive data continuously.
The CPU can read but not write to SCRDR. SCRDR is initialized to H'00 by a reset and in standby
or module standby mode.
Rev.6.00 Mar. 27, 2009 Page 487 of 1036
REJ09B0254-0600