HD6417727BP160CV Datasheet, PDF (324/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 10 On-Chip Oscillation Circuits
5. Bus clock (Bφ) frequency:
• Depending on the product, the clock ratio should be set to produce a frequency within one
of the ranges indicated below.
100 MHz products: 24 MHz to 50 MHz
160 MHz products: 24 MHz to 66.64 MHz
6. The frequency of the peripheral clock (Pφ) becomes:
• The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 2.
• For all products, the peripheral clock frequency (Pφ) should be set within the frequency
range 6 MHz to 33.34 MHz and no higher than the frequency of the CKIO pin.
• The peripheral clock frequency (Pφ) should be set to 13 MHz or higher if the USB function
module is used.
7. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
multiplication ratio of PLL circuit 1.
8. ×1, ×2, ×3, ×4, or ×6 can be used as the multiplication ratio of PLL circuit 1. ×1, ×1/2, ×1/3,
and ×1/4 can be selected as the division ratio of divider 1. ×1, ×1/2, ×1/3, ×1/4, and ×1/6 can
be selected as the division ratio of divider 2. Set the rate in the frequency control register. The
on/off state of PLL circuit 2 is determined by the mode.
Rev.6.00 Mar. 27, 2009 Page 266 of 1036
REJ09B0254-0600