HD6417727BP160CV Datasheet, PDF (725/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Bit 0—RX FIFO Half Size Full (RHF)
Bit 0: RHF
0
1
Description
Normal state
Rx FIFO half size interrupt
Section 21 Analog Front End Interface (AFEIF)
(Initial value)
Set condition:
1. The half of specified size with FFSZ (ACTR1) of receive data is accumulated into FIFO.
Clear condition:
1. Reset
2. Number of data in FIFO becomes smaller than the half of the size that is indicated by FFSZ
(ACTR1).
3. RE bit (ACTR1) is set to 0
(2) AFEIF Status Register 2 (ASTR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
DPEM RDETM
Initial value:
0
0
0
0
0
0
1
1
R/W: R
R
R
R
R
R
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DPE RDET
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W
R/W
ASTR2 is the register that is composed of interrupt status flag (2 bits) relating DAA control and
mask flag (2 bits) of interrupt signals for DAA control. Status flags shows statuses of ringing
detect interrupt, end of dial pulse output interrupt. Interrupt flags are cleared by 0 write after read
action of this register. Each Interrupt signal are able to be masked by each interrupt masks.
Bit 9—Dial Pulse End Interrupt Mask (DPEM)
Bit 9: DPEM
0
1
Description
Interrupt enable
Interrupt mask
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 667 of 1036
REJ09B0254-0600