HD6417727BP160CV Datasheet, PDF (831/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
25.2.4 LCDC Scan Mode Register (LDSMR)
LDSMR selects whether or not to enable the hardware rotation function that is used to rotate the
LCD panel, and sets the burst length for the system memory (VRAM) obtained for display.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
— ROT —
—
— AU1 AU0 —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R
R
R R/W R/W R
R
R
R
R
R
R
R
Bits 15, 14, 12 to 10, and 7 to 0—Reserved
Bit 13—Rotation Module Select (ROT): Selects whether or not to rotate the display by
hardware. Note that the following restrictions are applied to rotation.
• An STN or TFT panel must be used. A DSTN panel is not allowed.
• The maximum horizontal (internal scan direction of the LCD panel) width of the LCD panel is
320.
• Set a binary exponential that exceeds the display size in LDLAOR. (For example, select 256
when a 320 × 240 panel is rotated to be used as a 240 × 320 panel and the horizontal width of
the image is 240 bytes.)
Bit 13
ROT
0
1
Description
Not rotated
(Initial value)
Rotated 90 degrees rightwards (left side of image is displayed on the upper side of the
LCD module)
Bits 9 and 8—Access Unit Select (AU1 and AU0): Select the unit for accessing VRAM. This bit
is valid only when the ROT bit is set to 1 (rotation is performed). When the ROT bit is cleared to
0, 16-burst operation is performed regardless of the AU bits.
Bit 9
AU1
0
1
Bit 8
AU0
0
1
0
1
Description
4-burst operation
8-burst operation
16-burst operation
32-burst operation
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 773 of 1036
REJ09B0254-0600