HD6417727BP160CV Datasheet, PDF (165/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 3 Memory Management Unit (MMU)
3.3.2 TLB Indexing
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits 4 to 0 in PTEH are used as the index number. The index number can be
generated in two different ways depending on the setting of the IX bit in MMUCR.
1. When IX = 0, VPN bits 16 to 12 alone are used as the index number
2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate the index
number
The method 1 is used to prevent lowered TLB efficiency that results when multiple processes run
simultaneously in the same logical address space (multiple virtual memory) and a specific entry is
selected by indexing of each process. Figures 3.6 and 3.7 show the indexing schemes.
Virtual address
31
17 16 12 11
0
PTEH register
31
VPN
10 7
0
0 ASID
Index
Exclusive-OR
Ways 0 to 3
ASID(4−0)
0 VPN(31−17) VPN(11−10) ASID(7−0) V PPN(31−10) PR(1−0) SZ C D SH
31
Address array
Data array
Figure 3.6 TLB Indexing (IX = 1)
Rev.6.00 Mar. 27, 2009 Page 107 of 1036
REJ09B0254-0600