HD6417727BP160CV Datasheet, PDF (682/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
20.2.9 Interrupt Enable Register (SIIER)
This register allows SIOF interrupt resources to issue interrupt to CPU. When 1 is written to each
bit, corresponding interrupt is issued by SIOF. This register is initialized at power on reset, or
software reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— TCRDYE TFEMPE TDREQE — RCRDYE RFFULE RDREQE
0
0
0
0
0
0
0
0
R*
R/W
R/W
R/W
R*
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
— FSERRE TFOVRE TFUDRE RFUDRE RFOVRE
Initial value:
0
0
0
0
0
0
0
0
R/W: R*
R*
R*
R/W
R/W
R/W
R/W
R/W
Note: * 0 should be written into these bits. Otherwise the operation is unpredictable.
Bits 15, 11, and 7 to 5—Reserved
Bit 14—Transmit Control Data Ready Enable (TCRDYE)
Bit 14: TCRDYE
0
1
Description
Disable interrupt of transmit control data ready
(Initial value)
Enable interrupt of transmit control data ready (control interrupt)
Bit 13—Transmit FIFO Empty Enable (TFEMPE)
Bit 13: TFEMPE
0
1
Description
Disable interrupt of transmit FIFO empty
Enable interrupt of transmit FIFO empty (control interrupt)
(Initial value)
Bit 12—Transmit Data Transfer Request Enable (TDREQE)
Bit 12: TDREQE
0
1
Description
Disable interrupt of transmit data transfer request enable
(Initial value)
Enable interrupt of transmit data transfer request enable (transmit interrupt)
Rev.6.00 Mar. 27, 2009 Page 624 of 1036
REJ09B0254-0600