HD6417727BP160CV Datasheet, PDF (275/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
Bit 12—DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle
condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 12:
SCMFDB
0
1
Description
The DMAC cycle condition for channel B does not match
The DMAC cycle condition for channel B matches
(Initial value)
Bit 11—PC Trace Enable (PCTE): Enables PC trace.
Bit 11: PCTE
0
1
Description
Disables PC trace
Enables PC trace
(Initial value)
Bit 10—PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
Bit 10: PCBA
0
1
Description
PC break of channel A is set before instruction execution
PC break of channel A is set after instruction execution
(Initial value)
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Data Break Enable B (DBEB): Selects whether or not the data bus condition is included
in the break condition of channel B.
Bit 7: DBEB
0
1
Description
No data bus condition is included in the condition of channel B
The data bus condition is included in the condition of channel B
(Initial value)
Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
Bit 6: PCBB
0
1
Description
PC break of channel B is set before instruction execution
PC break of channel B is set after instruction execution
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 217 of 1036
REJ09B0254-0600