HD6417727BP160CV Datasheet, PDF (905/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 27 I/O Ports
27.3 Ports A to C, E, J, K
Each pin has an input pullup MOS, which is controlled by Port A to C, E, J, K Control Register in
PFC.
27.3.1 Ports A to C, E, J, K Data Rgister (PADR, PBDR, PCDR, PEDR, PJDR, PKDR)
Bit:
Initial value:
R/W:
7
Px7DT
0
R/W
6
Px6DT
0
R/W
5
Px5DT
0
R/W
4
Px4DT
0
R/W
3
Px3DT
0
R/W
2
Px2DT
0
R/W
1
Px1DT
0
R/W
0
Px0DT
0
R/W
Ports A to C, E, J, K Data Register (PADR, PBDR, PCDR, PEDR, PJDR, PKDR) is an 8-bit
read/write register that stores data for pins PTx7 to PTx0. Px7DT to Px0DT bit corresponds to
PTx7 to PTx0 pin. When the pin function is general output port, if the port is read, the value of the
corresponding PADR, PBDR, PCDR, PEDR, PJDR and PKDR bit is returned directly. When the
function is general input port, if the port is read, the corresponding pin level is read. Table 27.2
shows the function of PADR, PBDR, PCDR, PEDR, PJDR, PKDR.
PADR, PBDR, PCDR, PEDR, PJDR, PKDR is initialized to H'00 by a power-on reset. When
ASEMD0 is equal to 1, after PDCR and PEDR are initialized to H'00, the general input port
function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are
fetched. It retains its previous value in standby mode and sleep mode, and by a manual reset.
Table 27.2 Read/Write Operation of the Ports A to C, E, J, K Data Register
PxnMD1 PxnMD0 Pin State
Read
Write
0
0
Other function PxDR value Value is written to PxDR, but does not affect
pin state.
1
Output
PxDR value Write value is output from pin.
1
0
Input (Pullup Pin state
Value is written to PxDR, but does not affect
MOS: on)
pin state.
1
Input (Pullup Pin state
Value is written to PxDR, but does not affect
MOS: off)
pin state.
(n = 0 to 7)
(x = A to C, E, J, K)
Rev.6.00 Mar. 27, 2009 Page 847 of 1036
REJ09B0254-0600