HD6417727BP160CV Datasheet, PDF (822/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
Note: When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower-order
bit lines should be connected to GND or to the lowest bit from which data is output.
25.1.2 Block Diagram
Figure 25.1 shows a block diagram of LCDC.
LCLK
Bus clock (Bφ)
Peripheral clock (Pφ)
Peripheral
bus
Clock
generator
clk
512 bytes
Pallet ram
Register
LCDC
Power control
Li bus interface
Li bus
Figure 25.1 Block Diagram
Line buffer
2.4 kbytes
CL1
CL2
FLM
LCD 15−0
DON
VCPWC
VEPWC
M/DISP
Rev.6.00 Mar. 27, 2009 Page 764 of 1036
REJ09B0254-0600