HD6417727BP160CV Datasheet, PDF (1045/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 32 Electrical Characteristics
32.3.13 AFEIF Module Signal Timing
Table 32.18 AFEIF Module Signal Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item
Symbol Min
Max
AFE_SCLK clock input cycle time
t_ASCYC
8 × t_PCYC
AFE_SCLK input high-level width
t_ASWH
0.4 × t_ASCYC
AFE_SCLK input low-level width
t_ASWL
0.4 × t_ASCYC
AFE_FS input time
t_AFSD
0
AFE_TXOUT output delay time
t_ATDD
⎯
AFE_RXIN input setup time
t_ARDS
20
AFE_RXIN input hold time
t_ARDH
2 × t_PCYC + 20
AFE_HC1 output delay time
t_AHCD
⎯
AFE_RLYC output delay time
t_ARLYD
⎯
Note: t_PCYC is the cycle time (ns) of the peripheral clock (Pφ).
⎯
⎯
⎯
50
t_PCYC + 20
⎯
⎯
3 × t_PCYC + 20
t_PCYC + 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.6.00 Mar. 27, 2009 Page 987 of 1036
REJ09B0254-0600