HD6417727BP160CV Datasheet, PDF (297/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Bit 2: MSTP5
0
1
Section 9 Power-Down Modes and Software Reset
Description
ADC runs
Clock supply to ADC halted, and all registers initialized
(Initial value)
Bit 1—Module Stop 4 (MSTP4): Specifies halting the clock supply to the serial communication
interface SCI (SCIF) with FIFO. When the MSTP4 bit is set to 1, the clock supply to the SCIF is
halted
Bit 1: MSTP4
0
1
Description
SCIF runs
Clock supply to SCI2 (SCIF) halted
(Initial value)
Bit 0— Reserved: This bit is always read as 0. The write value should always as 0.
9.2.3 Standby Control Register 3 (STBCR3)
The standby control register 3 (STBCR3) is an 8-bit readable/writable register that controls
standby operation for the on-chip supporting modules. STBCR3 is initialized to H'00 by a power-
on reset.
Bit: 7
6
5
4
3
2
1
0
MSTP17 — MSTP15 MSTP14 MSTP13 — MSTP11 MSTP10
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7— Module Stop 17 (MSTP17): Specifies halting the clock supply to the serial IO with FIFO
interface (SIOF). When the MSTP17 bit is set to 1, the clock supply to the serial IO with FIFO
interface (SIOF) is halted.
Bit 7: MSTP17
0
1
Description
SIOF runs
Clock supply to SIOF halted
(Initial value)
Bit 6— Reserved: This bit is always read as 0. The write value should always as 0.
Rev.6.00 Mar. 27, 2009 Page 239 of 1036
REJ09B0254-0600