HD6417727BP160CV Datasheet, PDF (330/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 10 On-Chip Oscillation Circuits
10.6.2 Register Configurations
The WDT has two registers that select the clock, switch the timer mode, and perform other
functions. Table 10.5 shows the WDT register.
Table 10.5 Register Configuration
Name
Abbreviation R/W Initial Value Address
Access Size
Watchdog timer counter WTCNT
R/W* H'00
H'FFFFFF84 R: 8;
W: 16*
Watchdog timer control/ WTCSR
status register
R/W* H'00
H'FFFFFF86 R: 8;
W: 16*
Note: * Write with a word access. Write H'5A and H'A5, respectively, in the upper bytes. Byte or
longword writes are not possible. Read with a byte access.
10.7 WDT Registers
10.7.1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit read/write counter that increments on the
selected clock. The WTCNT differs from other registers in that it is more difficult to write to. See
section 10.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset
in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The
WTCNT counter is initialized to H'00 by a power-on reset through the RESETP pin. Use a word
access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read
WTCNT.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev.6.00 Mar. 27, 2009 Page 272 of 1036
REJ09B0254-0600