HD6417727BP160CV Datasheet, PDF (689/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
20.3.2 Serial Timing
(1) SIOFSYNC
SIOFSYNC is the frame sync signal, and supports the two modes shown below.
• The pulse with 1 bit width which shows the first of the sync pulse frame.
• The pulse with 1/2 frame width, which shows left channel in L/R stereo data as high and right
channel as low.
Figure 20.3 shows synchronized timing as SIOFSYNC. Figure 20.3(a) shows the case for master
mode 1, slave mode 1, and slave mode 2. Figure 20.3(b) shows the case for master mode 2.
(a) At the synch pulse
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
(b) At the L/R
First bit data (MSB)
1 bit delay
1 frame
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
Lch. first bit data (MSB)
Rch. first bit data (MSB)
1/2 frame length
No delay
1/2 frame length
Figure 20.3 SIOF Serial Data Synchronized Timing
Rev.6.00 Mar. 27, 2009 Page 631 of 1036
REJ09B0254-0600