HD6417727BP160CV Datasheet, PDF (458/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.3.2 DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip supporting modules that are neither the source
nor the destination. There are three types of transfer requests, an auto request, an external request
and an on-chip module request. The request mode is selected with the RS3 to RS0 bits in the
DMA channel control registers 0 to 3 (CHCR0 to CHCR3).
Auto-Request Mode: When no transfer request signal is input from an external source, such as
transfer between memories or between memory and an on-chip supporting module on which a
transfer request is disabled, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits in CHCR0 to CHCR3 and the DME bit in
DMAOR are set to 1, a transfer is started. At this time, the TE bits in CHCR0 to CHCR3 and the
NMIF bit in DMAOR should be all 0.
External Request Mode: A transfer is started by the transfer request signal (DREQ) from an
external device. Choose one of the modes shown in table 14.3 according to the application system.
If DREQ is input when the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0), a
DMA transfer starts. Select whether DREQ is detected on the falling edge or low level with the
DS bit in CHCR0 (level detection when DS = 0, edge detection when DS = 1).
The source of the transfer request does not have to be the data transfer source or destination.
Table 14.3 Selecting External Request Modes with the RS Bits
RS3 RS2 RS1 RS0 Address Mode Source
Destination
0
0
0
0
Dual address Arbitrary*
mode
Arbitrary*
1
0
Single address External memory, External device with
mode
memory-mapped DACK
external device
1
External device with External memory,
DACK
memory-mapped
external device
Note: * External memory, memory-mapped external device, on-chip memory, on-chip supporting
module (excluding DMAC, UBC, and BSC)
On-Chip Module Request Mode: A transfer is started by the transfer request signal (interrupt
request signal) from an on-chip supporting module. This mode cannot be set in case of 16-byte
transfer. There are eight types of transfer request signals, a receive data full interrupt (RXI) and a
transmit data empty interrupt (TXI) from the serial communication interface (SCIF), an A/D
conversion end interrupt (ADI) from the A/D converter, an compare-match timer interrupt (CMI)
Rev.6.00 Mar. 27, 2009 Page 400 of 1036
REJ09B0254-0600