HD6417727BP160CV Datasheet, PDF (387/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 12.2.4, Wait
State Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing
shown in figure 12.9.
T1
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
BS
Figure 12.9 Basic Interface Wait Timing (Software Wait Only)
When software wait insertion is specified by WCR2, the external wait input WAIT signal is also
sampled. TO input low level signal to WAIT, set the WAITSEL bit of the WCR1 register to 1.
WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software wait.
Rev.6.00 Mar. 27, 2009 Page 329 of 1036
REJ09B0254-0600