HD6417727BP160CV Datasheet, PDF (609/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 18 Smart Card Interface
18.3.4 Register Settings
Table 18.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or
0 must be set to the indicated value. The settings for the other bits are described below.
Table 18.3 Register Settings for the Smart Card Interface
Register
SCSMR
SCBRR
SCSCR
SCTDR
SCSSR
Address
H'FFFFFE80
H'FFFFFE82
H'FFFFFE84
H'FFFFFE86
H'FFFFFE88
Bit 7
C/A
BRR7
TIE
TDR7
TDRE
Bit 6
0
BRR6
RIE
TDR6
RDRF
SCRDR H'FFFFFE8A RDR7 RDR6
SCSCMR H'FFFFFE8C —
—
Note: Dashes indicate unused bits.
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
FER/
ERS
RDR4
—
Bit 3
1
BRR3
0
TDR3
PER
RDR3
SDIR
Bit 2
0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
BRR1
CKE1
TDR1
0
RDR1
—
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
1. Setting the serial mode register (SCSMR): The C/A bit selects the set timing of the TEND flag,
and selects the clock output state with the combination of bits CKE1 and CKE0 in the serial
control register (SCSCR). Set the O/E bit to 0 when the IC card uses the direct convention or
to 1 when it uses the inverse convention. Select the on-chip baud rate generator clock source
with the CKS1 and CKS0 bits (see section 18.3.5, Clock).
2. Setting the bit rate register (SCBRR): Set the bit rate. See section 18.3.5, Clock, to see how to
calculate the set value.
3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do
for the ordinary SCI0. See section 17, Serial Communication Interface (SCI), for more
information. The CKE0 bit specifies the clock output. When no clock is output, set 0; when a
clock is output, set 1.
4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both set to 0 for
IC cards that use the direct convention and both to 1 when the inverse convention is used. The
SMIF bit is set to 1 for the smart card interface.
Figure 18.4 shows sample waveforms for register settings of the two types of IC cards (direct
convention and inverse convention) and their start characters.
In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and
communication is LSB first. The start character data is H'3B. The parity bit is even (from the
smart card standards), and thus 1.
Rev.6.00 Mar. 27, 2009 Page 551 of 1036
REJ09B0254-0600