HD6417727BP160CV Datasheet, PDF (179/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 3 Memory Management Unit (MMU)
3.5.5
Processing Flow in Event of MMU Exception (Same Processing Flow for Address
Error)
MMU Exception in the Instruction Fetch Mode
IF ID EX MA WB
ID EX MA WB
ID EX MA WB
Handler transition
processing
NOP
NOP
MMU exception handler
IF ID EX MA WB
: Exception source stage
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
NOP = No operation
Figure 3.12 MMU Exception Signals in Instruction Fetch
Rev.6.00 Mar. 27, 2009 Page 121 of 1036
REJ09B0254-0600