HD6417727BP160CV Datasheet, PDF (232/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 7 Interrupt Controller (INTC)
Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
Priority
within IPR
Setting Default
Unit
Priority
NMI
H'1C0 (H'1C0)
16
—
—
High
H-UDI
H'5E0 (H'5E0)
15
—
—
IRQ
IRQ0
H'200–3C0* (H'600) 0–15 (0)
IPRC (3–0) —
IRQ1
H'200–3C0* (H'620) 0–15 (0)
IPRC (7–4) —
IRQ2
H'200–3C0* (H'640) 0–15 (0)
IPRC (11–8) —
IRQ3
H'200–3C0* (H'660) 0–15 (0)
IPRC (15–12) —
IRQ4
H'200–3C0* (H'680) 0–15 (0)
IPRD (3–0) —
IRQ5
H'200–3C0* (H'6A0) 0–15 (0)
IPRD (7–4) —
PINT PINT0–7 H'200–3C0* (H'700) 0–15 (0)
IPRD (15–12) —
PINT8–15 H'200–3C0* (H'720) 0–15 (0)
IPRD (11–8) —
DMAC DEI0
H'200–3C0* (H'800) 0–15 (0)
IPRE (15–12) High
DEI1
H'200–3C0* (H'820)
DEI2
H'200–3C0* (H'840)
DEI3
H'200–3C0* (H'860)
Low
SCIF ERI2
H'200–3C0* (H'900) 0–15 (0)
IPRE (7–4) High
RXI2
H'200–3C0* (H'920)
BRI2
H'200–3C0* (H'940)
TXI2
H'200–3C0* (H'960)
Low
ADC
ADI
H'200–3C0* (H'980) 0–15 (0)
IPRE (3–0) —
LCDC LCDCI H'200–3C0* (H'9A0) 0–15 (0)
IPRF(11–8) —
SIOF SIFERI H'200–3C0* (H'B00) 0–15 (0)
IPRF(3–0)
High
SIFTXI H'200–3C0* (H'B20) 0–15 (0)
SIFRXI H'200–3C0* (H'B40) 0–15 (0)
SIFCCI H'200–3C0* (H'B60) 0–15 (0)
Low
USBH USBHI H'200–3C0* (H'A00) 0–15 (0)
IPRG(15–12) —
USBF USBFI0 H'200–3C0* (H'A20) 0–15 (0)
IPRG(11–8) High
USBFI1 H'200–3C0* (H'A40) 0–15 (0)
IPRG(7–4) Low
AFEIF AFEIFI H'200–3C0* (H'A 60) 0–15 (0)
IPRG(3–0) —
Low
Rev.6.00 Mar. 27, 2009 Page 174 of 1036
REJ09B0254-0600