HD6417727BP160CV Datasheet, PDF (94/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
Table 2.5 DSR Register Bits
Bit
31–8
7
6
5
4
3–1
0
Name (Abbreviation) Function
Reserved bits
0: Always read out; always use 0 as a write value
Signed greater than bit
(GT)
Indicates that the operation result is positive
(excepting 0), or that operand 1 is greater than
operand 2
1: Operation result is positive, or operand 1 is greater
Zero bit (Z)
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or equivalence
Negative bit (N)
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is
smaller
Overflow bit (V)
Indicates that the operation result has overflowed
1: Operation result has overflowed
Status selection bits (CS) Designate the mode for selecting the operation result
status set in the DC bit
Do not set either 110 or 111
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed above mode
DSP status bit (DC)
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status not realized (unrealized)
1: Designated mode status realized
Rev.6.00 Mar. 27, 2009 Page 36 of 1036
REJ09B0254-0600