HD6417727BP160CV Datasheet, PDF (13/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

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641 20.3.7 Procedures for Transmit or Receive
(1) Transmitting in Master
Figure 20.9 Example of Transmit Operation
in Master
Revised Version
No.
Time chart
Start
Settting of SIMDR register,
1 _{SIMCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
No.
Time chart
Start
Settting of SIMDR register,
1 _{SISCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
642
643
(2) Receiving in Master
Figure 20.10 Example of Receive
Operation in Master
No.
Time chart
Start
Settting of SIMDR register,
1 _{SIMCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
(3) Transmitting in Slave
Figure 20.11 Example of Transmit
Operation in Slave
No.
Time chart
Start
Settting of SIMDR register,
1 _{SIMCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
No.
Time chart
Start
Settting of SIMDR register,
1 _{SISCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
No.
Time chart
Start
Settting of SIMDR register,
1 _{SISCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
644
(4) Receiving in Slave
Figure 20.12 Example of Receive
Operation in Slave
No.
Time chart
Start
Settting of SIMDR register,
1 _{SIMCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
No.
Time chart
Start
Settting of SIMDR register,
1 _{SISCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
650 (5) A Case of 16 bits Stereo (No.2)
Figure 20.17 Transmit or Receive Timing
(16 bits stereo 2)
680
Setting: TRMD = 01, REDG = 1,
TDLE = 1, TDLA3 to TDLA0 = 0000,
RDLE = 1, RDLA3 to RDLA0 = 0001,
CD0E = 0, CD0A3 to CD0A0 = 0000,
FL = 1101 (frame length 64 bits),
TDRE = 1, TDRA3 to TDRA0 = 0010,
RDRE = 1, RDRA3 to RDRA0 = 0011,
CD1E = 0, CD1A3 to CD1A0 = 0000
Setting: TRMD = 11, REDG = 1,
TDLE = 1, TDLA3 to TDLA0 = 0000,
RDLE = 1, RDLA3 to RDLA0 = 0001,
CD0E = 0, CD0A3 to CD0A0 = 0000,
FL = 1101 (frame length 64 bits),
TDRE = 1, TDRA3 to TDRA0 = 0010,
RDRE = 1, RDRA3 to RDRA0 = 0011,
CD1E = 0, CD1A3 to CD1A0 = 0000
22.1.1 Block Diagram
Figure 22.1 Block Diagram of USB PIN
Multiplexer
USB2P, USB2M, USB1P, USB1M
USB2_P, USB2_M, USB1_P, USB1_M
Rev.6.00 Mar. 27, 2009 Page xi of lvi
REJ09B0254-0600