HD6417727BP160CV Datasheet, PDF (429/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 13 Li Bus State Controller (LBSC)
13.1.5 Wait State Control Register 1 (WCR1)
Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of
idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bit:
Initial value:
R/W:
15
WAIT
SEL
0
R/W
14
13
12
11
10
9
8
— A6IW1 A6IW0 A5IW1 A5IW0 A4IW1 A4IW0
0
1
1
1
1
1
1
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
A3IW1 A3IW0 A2IW1 A2IW0 —
Initial value: 1
1
1
1
0
R/W: R/W R/W R/W R/W
R
2
1
0
— A0IW1 A0IW0
0
1
1
R
R/W R/W
Bits 15 to 8 and 5 to 0 —Not referenced
Bits 7 and 6— Area 3 Idle Setting between Cycles (A3IW1, A3IW0): Specifies the number of
idle state cycles to insert between bus cycles when switching from a read address in area 3 of the
physical space to a write address in another space or within the same space.
Bit 7: A3IW1
0
1
Bit 6: A3IW0
0
1
0
1
Description
1 idle state cycle inserted
1 idle state cycle inserted
2 idle state cycle inserted
3 idle state cycle inserted
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 371 of 1036
REJ09B0254-0600