HD6417727BP160CV Datasheet, PDF (628/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2 Register Descriptions
19.2.1 Receive Shift Register 2 (SCRSR2)
The receive shift register 2 (SCRSR2) receives serial data. Data input at the RxD2 pin is loaded
into the SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form.
When one byte has been received, it is automatically transferred to the SCFRDR2, which is a
receive FIFO data register 2. The CPU cannot read or write the SCRSR2 directly.
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
19.2.2 Receive FIFO Data Register 2 (SCFRDR2)
The 16-byte receive FIFO data register 2 (SCFRDR2) stores serial receive data. The SCIF
completes the reception of one byte of serial data by moving the received data from the receive
shift register 2 (SCRSR2) into the SCFRDR2 for storage. Continuous receive is enabled until 16
bytes are stored.
The CPU can read but not write the SCFRDR2. When data is read without received data in the
SCFRDR2, the value is undefined. When the received data in this register becomes full, the
subsequent serial data is lost.
Bit: 7
6
5
4
3
2
1
0
R/W: R
R
R
R
R
R
R
R
Rev.6.00 Mar. 27, 2009 Page 570 of 1036
REJ09B0254-0600