HD6417727BP160CV Datasheet, PDF (486/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
CK
Internal
address bus
Internal
data bus
SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2
SAR2 data
SAR2+2 data
SAR2+4 data
SAR2+6 data
First transfer of
channel 2
SAR2 output
DAR2 output
Second transfer
SAR2+2 output
DAR2 output
Third transfer
SAR2+4 output
DAR2 output
Fourth transfer Fifth transfer
SAR2+6 output
DAR2 output
SAR2 reload
SAR2 output
DAR2 output
Figure 14.25 Timing Chart of Source Address Reload Function
The reload function can be used for the 8-, 16- and 32-bit data transfer.
DMATCR2, which specifies a transfer count, is incremented by 1 each time a transfer ends
regardless of the reload function setting. Consequently, be sure to specify the value multiple of
four in DMATCR2 when the reload function is on. If other values are specified, correct operation
is not guaranteed.
The counters that count transfers of four times for the reload function are reset by clearing the
DME bit in DMAOR or the DE bit in CHCR2, by setting the transfer end flag (TE bit in CHCR2),
by inputting an NMI, besides by a reset or in standby mode. However, the SAR2, DAR2,
DMATCR2 registers are not reset. Therefore, the above reset source is generated, some counters
are initialized but some are not in the DMAC, which may cause a malfunction when the DMAC is
restarted. To avoid this problem, if a reset source except the TE bit setting is generated when the
reload function is used, set SAR2, DAR2, and DMATCR2 again.
Rev.6.00 Mar. 27, 2009 Page 428 of 1036
REJ09B0254-0600