HD6417727BP160CV Datasheet, PDF (364/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Bit 2—Refresh Control (RFSH): The RFSH bit determines whether or not the refresh operation
of the synchronous DRAM is performed. The timer for generation of the refresh request frequency
can also be used as an interval timer.
Bit 2: RFSH
0
1
Description
No refresh
Refresh
(Initial value)
Bit 1—Refresh Mode (RMODE): The RMODE bit selects whether to perform an ordinary
refresh or a self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, a CAS-
before-RAS refresh or an auto-refresh is performed on synchronous DRAM at the period set by
the refresh-related registers RTCNT, RTCOR and RTCSR. When a refresh request occurs during
an external bus cycle, the bus cycle will be ended and the refresh cycle performed. When the
RFSH bit is 1 and this bit is also 1, the synchronous DRAM will wait for the end of any executing
external bus cycle before going into a self-refresh. All refresh requests to memory that is in the
self-refresh state are ignored.
Bit 1: RMODE
0
1
Description
CAS-before-RAS refresh (RFSH must be 1)
Self-refresh (RFSH must be 1)
(Initial value)
Bit 0—Reserved: This bit is always read as 0. The write value should always be 0.
12.2.6 PCMCIA Control Register (PCR)
The PCMCIA control register (RCR) specifies the assert/negate timing of the OE and WE signals
(RD and WE1 pins of this LSI) for the PCMCIA interface connected to areas 5 and 6. Note that
the assertion widths of OE and WE are set using the wait control bits of the WCR2 register.
The PCR register is a 16-bit read/write register. It is initialized at a power-on reset to H'0000.
However, the register is not initialized and the contents remain unchanged at a manual reset and
when in standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
A6 A5 —
W3 W3
— A5 A6 A5 A6 A5 A5 A6 A6 A5 A5 A6 A6
TED2 TED2 TEH2 TEH2 TED1 TED0 TED1 TED0 TEH1 TEH0 TEH1 TEH0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.6.00 Mar. 27, 2009 Page 306 of 1036
REJ09B0254-0600