HD6417727BP160CV Datasheet, PDF (454/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.2.6 DMA Operation Register (DMAOR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
PR1 PR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit: 7
6
5
4
3
2
—
—
—
—
—
AE
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R R/(W)*
Note: * Only a write of 0 after a read of 1 is enabled for the AE and NMIF bits.
1
NMIF
0
R/(W)*
0
DME
0
R/W
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMAC
transfer mode.
This register is initialized to 0 by a power-on reset. The previous values are held in standby mode.
Bits 15 to 10—Reserved: These bits are always read as 0 and should only be written with 0.
Bits 9 and 8—Priority Mode 1, 0 (PR1 and PR0): PR1 and PR0 select the priority level between
channels when transfer requests are generated for multiple channels simultaneously.
Bit 9: PR1
0
1
Bit 8: PR0
0
1
0
1
Description
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round-robin
(Initial value)
Bits 7 to 3—Reserved: These bits are always read as 0 and should only be written with 0.
Rev.6.00 Mar. 27, 2009 Page 396 of 1036
REJ09B0254-0600