HD6417727BP160CV Datasheet, PDF (401/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Tp
TRr TRrw TRrw (Tpc)
CKIO,
CKIO2
CKE
CSn
RAS
CAS
RD/WR
Figure 12.19 Synchronous DRAM Auto-Refresh Timing
2. Self-Refreshing
Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are
generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE
bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low.
Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is
cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command
issuance is disabled for the number of cycles specified by the TPC bits in MCR. Self-refresh
timing is shown in figure 12.20. Settings must be made so that self-refresh clearing and data
retention are performed correctly, and auto-refreshing is performed at the correct intervals. When
self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby
mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and
RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-
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