HD6417727BP160CV Datasheet, PDF (352/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Bit 12—High-Z Control (HIZCNT): Specifies the state of the RAS and the CAS signals at
standby and bus right release.
Bit 12: HIZCNT
0
1
Description
The RAS and the CAS signals are high-impedance state (High-Z) at standby
and bus right release.
(Initial value)
The RAS and the CAS signals are driven at standby and bus right release.
Bit 11—Endian Flag (ENDIAN): Samples the value of the external pin designating endian upon
a power-on reset. Endian for all physical spaces is decided by this bit, which is read-only.
Bit 11: ENDIAN
0
1
Description
(On reset) Endian setting external pin (MD5) is low. Indicates this LSI is set
as big endian.
(On reset) Endian setting external pin (MD5) is high. Indicates this LSI is set
as little endian.
Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst
ROM in physical space area 0. When burst ROM is used, set the number of burst transfers.
Bit 10: A0BST1
0
Bit 9: A0BST0
0
1
1
0
1
Description
Access area 0 as ordinary memory
(Initial value)
Access area 0 as burst ROM (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
Access area 0 as burst ROM (8 consecutive accesses).
Can be used when bus width is 8 or 16.
Access area 0 as burst ROM (16 consecutive
accesses). Can be used only when bus width is 8.
Rev.6.00 Mar. 27, 2009 Page 294 of 1036
REJ09B0254-0600