HD6417727BP160CV Datasheet, PDF (825/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
25.2 Register Descriptions
25.2.1 LCDC Input Clock Register (LDICKR)
This LCDC can select the bus clock (Bφ), the peripheral clock (Pφ), or the external clock as its
operation clock source. The selected clock source can be divided using an internal divider into a
clock of 1/1 to 1/16 and be used as the LCDC operating clock (DOTCLOCK). The clock output
from the LCDC is used to generate the synchronous clock output (CL2) for the LCD panel from
the operating clock selected in this register. The average frequency of CL2 can be calculated using
the formula below. The actual frequency, however, will differ depending on the type of LCD panel
and the bus width of the data output to the LCD panel. See section 25.4, Clock and LCD Data
Signal Examples, for details.
TFT panel
CL2 = DOTCLOCK
STN or DSTN panel
Monochrome: CL2 = (DOTCLOCK/data bus width of output to LCD panel)
Color: CL2 = 3 × (DOTCLOCK/data bus width of output to LCD panel)
Set this register so that the clock input to the LCDC is 50 MHz or less regardless of CL2.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
— ICKSEL ICKSEL —
—
—
—
—
—
— DCDR4 DCDR3 DCDR2 DCDR1 DCDR0
1
0
Initial value: 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
R/W: R
R R/W R/W R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Bits 15, 14, and 11 to 5—Reserved
Bits 13 and 12—Input Clock Select (ICKSEL1 and ICKSEL0): Set the clock source for
DOTCLOCK.
Bit 13
ICKSEL1
0
1
Bit 12
ICKSEL0
0
1
0
1
Description
Bus clock (Bφ) is selected
Peripheral clock (Pφ) is selected
External clock (LCLK) is selected
Reserved (setting prohibited)
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 767 of 1036
REJ09B0254-0600